R&D Tax Credit for Semiconductor & Chip Companies: CHIPS Act 2026 Guide

Published 2026-04-11

R&D Tax Credit for Semiconductor & Chip Companies: CHIPS Act 2026 Guide

Quick Answer

Semiconductor and chip manufacturing companies can claim significant R&D tax credits for activities ranging from process node advancement and fab process development to chip architecture design and packaging innovation. The federal R&D tax credit under Section 41 provides a dollar-for-dollar reduction in tax liability worth up to 10% of qualified research expenses (QREs), while the CHIPS and Science Act adds separate investment tax credits of up to 25% for qualifying semiconductor manufacturing facilities. Combined with state-level incentives in fabrication hubs like Arizona, Texas, Ohio, and Oregon, total potential savings can reach millions of dollars annually for companies with substantial R&D operations.

Key Takeaways

• Semiconductor R&D activities broadly qualify: Process node advancement (e.g., 5nm→3nm→2nm), lithography development, etch/deposition optimization, advanced packaging (chiplets, 3D stacking), and yield improvement experiments all meet the 4-part test for qualifying research activities.
• CHIPS Act + R&D credit stack: The CHIPS Act’s Section 48D Advanced Manufacturing Investment Credit (up to 25%) is separate from the Section 41 R&D credit — companies can claim both with proper expense allocation.
• Section 174 amortization makes credits more valuable: Since R&D expenses must be amortized over 5 years, the immediate dollar-for-dollar benefit of the R&D credit provides crucial cash flow relief.
• State credits amplify savings: Arizona (24%), Texas (franchise tax credit + sales tax exemption), Ohio, and Oregon offer substantial additional credits for semiconductor R&D operations.
• Both fabs and fabless companies qualify: Process engineers at fabs and chip designers at fabless companies can claim credits — the key is demonstrating technological uncertainty and experimentation.
• Documentation is critical: Fab experiment logs, yield analysis reports, engineering timesheets, and contract research agreements form the foundation of a defensible claim.

Qualifying Semiconductor R&D Activities

Process Node Development

Advancing semiconductor process nodes is inherently experimental. Each generation — from 7nm to 5nm, 3nm, and toward 2nm — involves resolving fundamental technological uncertainties:

• Lithography optimization: Developing EUV (extreme ultraviolet) lithography processes, multi-patterning techniques, and high-NA EUV implementation
• Etch and deposition refinement: Creating new plasma etch recipes, atomic layer deposition (ALD) processes, and chemical vapor deposition (CVD) techniques at smaller geometries
• Materials science research: Testing new gate dielectrics, channel materials (silicon-germanium, transition metal dichalcogenides), and interconnect metals
• Transistor architecture: Developing Gate-All-Around (GAA) FETs, CFET (Complementary FET) architectures, and novel device structures

Each of these activities involves systematic experimentation to resolve technical uncertainty — the core requirement for R&D tax credit qualification under the 4-part test.

Advanced Packaging R&D

The semiconductor industry increasingly relies on advanced packaging as a path to performance gains:

• Chiplet integration: Developing interconnect technologies (microbumps, hybrid bonding, silicon interposers) for multi-die systems
• 3D stacking: Through-silicon via (TSV) process development, thermal management solutions for stacked dies
• Heterogeneous integration: Combining different process nodes and materials in a single package
• Fan-out wafer-level packaging (FOWLP): Process development for density improvements and warpage control

These activities qualify because they involve designing and testing new processes where the outcome is not certain at the outset.

Fabless Chip Design Activities

Fabless semiconductor companies conduct substantial qualifying R&D even without fabrication facilities:

• Architecture and microarchitecture design: Developing novel processor architectures, accelerator designs, and memory subsystems
• RTL design and verification: Register-transfer level coding, formal verification, and emulation testing
• Physical design: Place-and-route optimization, timing closure, and power integrity analysis at advanced nodes
• Design-for-test (DFT): Creating built-in self-test (BIST) structures, scan chain insertion, and test pattern generation
• IP core development: Designing reusable semiconductor IP blocks for interfaces, processors, or analog circuits
• Silicon validation: First-silicon bring-up, characterization testing, and debug activities

Fab Operations and Yield Improvement

Operational activities within semiconductor fabs can qualify when they involve resolving technical uncertainty:

• Yield enhancement experiments: Systematic design of experiments (DOE) to improve wafer yields
• Process window optimization: Tightening process parameters for better uniformity and performance
• Equipment qualification: Developing new recipes for recently installed process tools
• Defect reduction: Root cause analysis and process modifications to eliminate systematic defects

Important: Routine production monitoring and standard maintenance do not qualify. The key distinction is whether the activity involves resolving technical uncertainty through experimentation. See our documentation checklist for guidance on tracking qualifying versus non-qualifying activities.

The CHIPS Act and R&D Tax Credits: How They Work Together

Section 48D: Advanced Manufacturing Investment Credit

The CHIPS and Science Act created a new 25% investment tax credit for qualified investments in semiconductor manufacturing facilities (Section 48D). Key details for 2026:

• Credit rate: 25% of qualified investment in semiconductor manufacturing property
• Eligible property: Manufacturing equipment, buildings, and structural components used in semiconductor production
• Phase-out: Begins in 2027 — making 2026 a critical year for maximizing benefits
• Apprenticeship requirements: Must meet prevailing wage and registered apprenticeship standards

Stacking CHIPS Act Credits with R&D Tax Credits

The Section 48D investment credit and Section 41 R&D credit are separate, stackable benefits:

Critical rule: You cannot include the same expense in both credit calculations. Capital expenditures qualifying for Section 48D must be excluded from QREs for Section 41, and vice versa. Proper expense allocation is essential — see our guide on Section 174 and R&D expensing for allocation strategies.

Section 174 Amortization: Impact on Semiconductor Companies

Since the Tax Cuts and Jobs Act changes took effect in 2022, domestic R&D expenses must be amortized over 5 years (15 years for foreign research) instead of being immediately deductible.

Why This Makes R&D Credits More Valuable

For semiconductor companies with large R&D budgets, Section 174 amortization creates a significant cash flow timing disadvantage. Consider a company with $50M in annual R&D spending:

• Pre-2022: $50M immediately deductible, reducing taxable income by $50M in Year 1
• Current law: Only $10M deductible in Year 1 (5-year straight-line amortization, half-year convention: $50M × 50% / 5 = $5M deduction in Year 1 under mid-year convention)

The R&D tax credit provides an immediate dollar-for-dollar offset against tax liability, regardless of the amortization schedule. This makes the credit substantially more valuable in the current tax environment.

Choosing Between ASC and Regular Method

Semiconductor companies should carefully evaluate which calculation method maximizes their credit:

• Regular Method: Better for companies with increasing R&D spending and substantial QREs relative to the 1984-1988 base period
• ASC Method: Better for established companies with stable or gradually increasing R&D budgets

Our Alternative Simplified Credit method guide provides detailed calculation examples for both approaches.

State R&D Credits for Semiconductor Hubs

Arizona

Arizona has become a major semiconductor hub (TSMC, Intel) and offers robust incentives:

• R&D Tax Credit: Up to 24% credit on increased R&D spending (calculated on the excess over a base amount)
• Quality Jobs Tax Credit: Up to $9,000 per qualifying new employee over 3 years
• Sales Tax Exemption: Manufacturing equipment and R&D equipment purchases are exempt from state transaction privilege tax

Texas

Texas semiconductor investments (Samsung, Texas Instruments, NXP) benefit from:

• Franchise Tax Credit: R&D credit against the Texas margin tax
• Sales Tax Exemption: Manufacturing and R&D equipment exempt from state and local sales tax (up to 8.25%)
• Chapter 313/Chapter 403: Property tax abatements for large manufacturing projects (being restructured)

Ohio

Intel’s $20B+ Ohio fab campus benefits from:

• Job Retention Tax Credit: Up to 15-year credit against state income tax
• Job Creation Tax Credit: Based on new payroll generated
• R&D Investment Tax Credit: Ohio offers a non-refundable credit for R&D investments

Oregon

Oregon’s “Silicon Forest” (Intel’s largest site) benefits from:

• R&D Tax Credit: Oregon’s research credit based on increased qualifying research expenses
• Strategic Investment Program (SIP): Property tax abatement for large capital investments
• Enterprise Zone exemptions: Additional property and income tax benefits

Quantifying Your R&D Credit: A Semiconductor Example

Consider a mid-size semiconductor company with the following annual R&D profile:

Federal Credit Calculation (ASC Method)

Under the Alternative Simplified Credit method:

• Credit = 14% × QREs in excess of 50% of average QREs for the 3 preceding years
• Assuming $28M average prior 3 years: Credit = 14% × ($30M - $14M) = $2,240,000 federal credit

Total Potential Savings

Documentation Best Practices for Semiconductor R&D Claims

Technical Documentation

Maintain contemporaneous records that demonstrate the 4-part test:

1. Project descriptions: Document the technological uncertainty being addressed (e.g., “Developing EUV lithography process for 2nm node metal patterning with target CD uniformity <1.5nm”)
2. Experiment logs: Record process parameters, test conditions, results, and conclusions for each experimental run
3. Design review minutes: Document technical challenges discussed, alternatives evaluated, and decisions made
4. Yield analysis reports: Track before/after yield improvements tied to specific process experiments

Financial Documentation

1. Engineering timesheets: Track time at the project level for process engineers, device physicists, and design engineers
2. Supply purchase records: Receipts for test wafers, chemicals, gases, packaging materials, and prototype components
3. Contract research agreements: Fully executed agreements with universities, national labs, or third-party testing facilities
4. Equipment allocation: For shared-use equipment, document the percentage of time used for qualifying R&D versus production

Substantiation During IRS Examination

The IRS has increased scrutiny of R&D credit claims, particularly for large manufacturers. Key steps to prepare:

• Maintain a contemporary business component analysis tying expenses to specific qualifying activities
• Ensure direct supervision and support of research is documented for overhead employees
• Prepare process of experimentation narratives for each major project
• Keep before-and-after documentation showing the technological knowledge gap being addressed

For a complete documentation framework, see our R&D tax credit documentation checklist.

Common Pitfalls for Semiconductor Companies

1. Including Section 48D Property in QREs

Capital investments that qualify for the CHIPS Act’s Section 48D credit cannot be included as QREs for the Section 41 R&D credit. Proper segregation of capital versus operating R&D expenses is essential.

2. Over-allocating Production Engineers to R&D

Not all fab engineering work qualifies. Routine process monitoring, standard recipe execution, and scheduled maintenance do not meet the 4-part test. Only activities involving genuine technical uncertainty and experimentation should be included.

3. Failing to Document the Technological Uncertainty

Semiconductor companies often assume their work is “obviously” R&D. However, the IRS requires specific documentation showing what technological uncertainty existed and how it was resolved through experimentation.

4. Missing State Credits

Many semiconductor companies focus solely on the federal credit and overlook valuable state incentives. Companies with operations in multiple states should evaluate each state’s credit independently.

5. Not Using the Payroll Tax Offset

Eligible startups (less than $5M in gross receipts and no more than 5 years of gross receipts) can offset up to $500,000 per year in FICA payroll taxes with the R&D credit. This is particularly relevant for semiconductor startups and spin-offs.

Steps to Claim Your Semiconductor R&D Credit

1. Identify qualifying activities: Map semiconductor projects to the 4-part test (permitted purpose, technological uncertainty, process of experimentation, technological in nature)
2. Allocate expenses: Track wages, supplies, and contract research by project, excluding production activities and Section 48D investments
3. Choose calculation method: Compare the Regular Method and ASC Method to determine which maximizes your credit
4. Prepare documentation: Maintain contemporaneous technical and financial records
5. File Form 6765: Complete and attach to your federal tax return — see our Form 6765 guide for step-by-step instructions
6. Claim state credits: File separately in each state where qualifying R&D was performed
7. Consider Section 48D coordination: If claiming the CHIPS Act investment credit, ensure proper expense segregation

Conclusion

Semiconductor and chip manufacturing companies are uniquely positioned to benefit from R&D tax credits. The inherently experimental nature of process development, chip design, and packaging innovation means substantial portions of engineering budgets can qualify. With the added momentum of the CHIPS Act and state-level incentives, the total potential savings for semiconductor companies can reach millions of dollars annually.

The key to maximizing your benefit is thorough documentation, proper expense allocation between the R&D credit and CHIPS Act incentives, and choosing the optimal credit calculation method. Don’t leave money on the table — every dollar invested in semiconductor R&D innovation deserves proper tax credit treatment.

Ready to calculate your potential R&D credit? Use our R&D Tax Credit Calculator to estimate your federal and state savings, or review our complete documentation checklist to prepare your claim.